Baseband communications systems involve the transmission of bits over an electrical or optical line. The transmitter sends the data bits in one of several formats, such as PAM (Pulse Amplitude Modulation) or NRZ (Non-Return to Zero) modulation. Modern systems carry data bits of multiple Giga-bit rates over electrical wire, back planes, board traces and/or over optical fibers. Examples are SAS and SATA disk data transfer protocols operating at 1.5 Gbps, 3 Gbps, 6 Gbps and 12 Gbps.
When the data bits are carried over the electrical or optical media, the signal is impaired by several effects. These include, among others: power supply noise; cross talk; frequency dependence of the channel transfer function; DC offset; and clock jitter, clock frequency, and phase offsets at the transmitter and receiver. It is the task of the receiver to recover the transmitted bits from the impaired received signal.
In receivers of SERDES systems, the high-speed line signal is sampled serially and the recovered bits are output in groups, in parallel, at a lower rate. For instance a SERDES for a 6 Gbps line rate might sample the line rate at 6 Gbps and output the recovered data to a 10-bit bus at 600 MHz or a 20-bit bus at 300 MHz.
In most analog SERDES receivers, the local bit recovery clock is carefully and precisely synchronized with the baud rate of the received signal. Then, at each receiver clock cycle, the signal is sampled at the center of the baud to recover the transmitted bit. Additional equalization may be applied to undo some of the channel distortion and to improve the BER (Bit Error Rate).
In most DSP (Digital Signal Processing) based asynchronous SERDES receivers, the local bit recovery clock is not synchronized, and instead the received analog signal is first sampled and digitized at the ADC (Analog to Digital Converter) using the DSP clock. A DSP interpolator is applied to recover the data bits, and its interpolation index is calculated by a DSP based TR (Timing Recovery) circuit. To this end, the received signal is sampled at a rate higher than the baud rate. The over sampling rate may be 1.5×, 2×, 3× or even 4× depending on the desired interpolation and timing tracking performance at the given signal impairments. Typically the asynchronous DSP clock frequency may be several hundreds or even thousands of ppm (parts per million) offset from the transmit clock.
To perform the data recovery, the TR circuit supplies a regularly updated interpolation index to the interpolator, which calculates the signal amplitude at that index. This calculated signal amplitude is then used to recover the transmitted data bit. Often this simply involves determining the sign of the interpolated signal at the desired interpolation index. In some systems an equalizer may be applied, which calculates an equalized amplitude from the interpolated amplitude. The equalizer may comprise a FFE (Feed Forward Equalizer) and/or a DFE (Decision Feedback Equalizer).
When the final SERDES system is validated, it is assessed in terms of its tolerance to SJ (Sinusoidal jitter) under various operating conditions. This is a characterization based on the BER (Bit Error Rate) of the received signal.
Digital timing control circuits in communications systems, such as a DPLL (Digital Phase Locked Loop), involve the calculation of a phase and/or frequency control signal in response to a timing error obtained from the received signal. In feedback control systems, the error is obtained from the signal after the phase and/or frequency adjustment has been applied. The feedback delay is typically defined as the time taken to calculate the timing error signal, to update the control signal based on the calculated timing error signal, and to apply the updated control signal to the incoming signal.
The delay is primarily due to pipelining stages in the digital control circuits, and is critical in the performance of the timing recovery. The digital control circuit involves the use of DSPs to calculate the control signal based on the detected error signal. The DSP functions in an ASIC implementation involve arithmetic circuits such as signal multipliers, signal comparators, and signal adders, which are synthesized into logic gates.
At high data rates, a high rate DSP clock must be applied for satisfactory loop tracking performance. The logic for the arithmetic circuits must be synthesized with a high speed library of gates and/or by applying pipelining stages.
For instance, in a DSP system, to recover data at a rate of 6 Gbps in an application such as SAS or SATA, it is necessary to perform loop tracking at DSP rates above 700 Msps. In other words, the DSP logic gates must be clocked at rates above 700 MHz. Consequently, the DSP arithmetic must be pipelined and fast library cell sets with Low VTs (Low Threshold Voltage) must be used in conjunction with logic gate libraries with channel sizes of 40 nm and 65 nm. The additional pipeline registers increase the power consumption per clock cycle, and the Low VT library cells draw increased static power. However, state of the art ASIC implementations for high speed data communication systems are specified with very tight power consumption and heat dissipation limits.
Thus, it is desirable to design high speed control circuits that draw less power and have lower latency. Also, improvements in the generation of control signals for timing recovery of the received signal are desirable.